Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA in 2005. Currently, Dr. Bhunia is a preeminent professor, director of the Warren B. Nelms Institute for the Connected World and Semmoto Chair Professor of Internet of Things in the department of Electrical and Computer Engineering at University of Florida, Gainesville, FL, USA. Earlier, Dr. Bhunia has served as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over twenty years of research and development experience with over 250 publications in peer-reviewed journals and premier conferences and ten edited or authored books (two upcoming) in the area of VLSI design, CAD and test techniques. His research interests include low power and robust design, hardware security and trust, adaptive nanocomputing and novel test methodologies. He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about three years. Dr. Bhunia received IEEE-CS TCVLSI Distinguished Research Award (2018), IBM Faculty Award (2013), National Science Foundation (NSF) career development award (2011), Semiconductor Research Corporation (SRC) technical excellence award (2005) as a team member, best paper award in ACM Transactions on Design Automation of Electronic Systems (TODAES 2017), best paper award in IEEE BioMedical Circuits and Systems Conference (BioCAS 2016), best paper award in International Conference on VLSI Design (VLSI Design 2012), best paper award in International Conference on Computer Design (ICCD 2004), best paper award in Latin American Test Workshop (LATW 2003), and best paper nomination in Asia and South Pacific Design Automation Conference (ASP-DAC 2006) and in Hardware Oriented Test and Security (HOST 2010), nomination for John S. Diekhoff Award, Case Western Reserve University (2010) and SRC Inventor Recognition Award (2009).
Dr. Bhunia has been serving as founding editor-in-chief in Journal of Hardware and Systems Security (HaSS), an associate editor of IEEE Transactions on CAD (TCAD), IEEE Transactions on Multi-Scale Computing Systems (TMSCS), ACM Journal of Emerging Technologies (JETC), and Journal of Low Power Electronics (JOLPE). He has served as a guest editor of IEEE Design & Test of Computers (2010, 2013), IEEE Computer Magazine (2016), IEEE Transcation on CAD (2015), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2014). He has served as co-program chair of IEEE IMS3TW 2011, IEEE NANOARCH 2013, IEEE VDAT 2014, and IEEE HOST 2015, and in the technical program committee of Design Automation Conference (2014-2015), Design Automation and Test in Europe (DATE 2006-2010), Hardware Oriented Trust and Security Symposium (HOST 2008-2010), IEEE/IFIP International Conference on VLSI (VLSI SOC 2008), Test Technology Educational Program (TTEP 2006-2008), International Symposium on Low Power Electronics and Design (ISLPED 2007-2008), IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH 2007-2010), IEEE International Conference on VLSI (ISVLSI 2008-2010), International Conference of VLSI Design as a track chair (2010) and in the program committee of International Online Test Symposium (IOLTS 2005). Dr. Bhunia has given tutorials on low-power and robust design and test in premier conference including International Test Conferences (ITC 2009), VLSI Test Symposium (VTS 2010), and Design Automation and Test in Europe (DATE 2009). He is a distinguished ACM speaker and a senior member of IEEE.
Email: swarup@ece.ufl.edu
DVP term expires December 2023
Presentations
Security of the Internet of Things: Are We Paranoid Enough?
Security has become a critical design challenge for modern electronic hardware. With the emergence of the Internet of Things (IoT) regime that promises exciting new applications from smart cities to connected autonomous vehicles, security has come to the forefront of the system-design process. Recent discoveries and reports on numerous security attacks on microchips and circuits violate the well-regarded concept of hardware trust anchors. It has prompted system designers to develop a wide array of design-for-security and test/validation solutions to achieve high-security assurance for electronic hardware, which supports the software stack. At the same time, emerging security issues and countermeasures have also led to interesting interplay between security, verification and interoperability. Verification of hardware for security and trust at different levels of abstraction is rapidly becoming an integral part of the system design flow. The global economic trend that promotes outsourcing of design and fabrication process to untrusted facilities coupled with the prevalent practice of system on chip design using untrusted third-party intellectual property blocks (IPs), has given rise to the critical need of trust verification of IPs, system-on-chip design, and fabricated chips. The talk will also cover a spectrum of security challenges for IoTs and describe emerging solutions in creating secure trustworthy hardware that can enable IoT security for the mass.
Innovations in IoT for a Safe, Secure, and Sustainable Future
Internet of Things (IoT) promises to usher in the fourth industrial revolution through an exponential growth of smart connected devices deployed in myriad application domains. It gives rise to new relationships between man and smart connected machines that might transform our everyday experiences. Such a transformation, however, builds on innovations at all levels in the IoT architecture – from edge devices to the cloud. In this talk, we will cover the IoT design practices and core technological challenges that need to be addressed to enable widespread deployment of IoT. We will focus on innovations in the areas of energy-efficiency, security, interoperability and intelligent decision making. Next, we will discuss several compelling applications of IoT that give unprecedented capability to us. In particular, we will cover applications of IoT in addressing some of the critical safety, security, and sustainability issues in our society.
Computing in Memory for Data-Intensive Kernels
Energy-efficiency has emerged as a major barrier in performance scalability for applications that require handling a large volume of data including analytics and informatics applications. For these applications, energy dissipation is primarily contributed by transportation of the data from off-chip memory to on-chip computing elements—a limitation referred to as the Von-Neumann bottleneck. In such a scenario, the traditional approach to parallel computing or hardware acceleration inside a processor brings only a minor improvement in total energy and throughput. Hence, there is a critical need to develop an efficient hardware accelerator for the ever-growing set of data-intensive applications. This talk focuses on a novel scalable memory-centric reconfigurable accelerator architecture, called MAHA, for data-intensive applications with associated application-mapping software framework tailored to the features of the architectural fabric. MAHA is a spatio-temporal mixed-granular malleable hardware reconfigurable framework, which utilizes the memory for both storage and computation (hence, malleable). It exploits high-density and low access-time/energy of nanoscale memory and implements a distinct instruction-set architecture optimized for data-intensive applications including support for lookup and complex fused operations. We analyze the effectiveness of MAHA for text analytics applications, such as Lucene as well as several common analytics kernels (such as, naive Bayesian classifier, k-Means clustering) and discuss the effect of in-accelerator compression/decompression to further improve energy-efficiency in MAHA. Finally, we propose the development of a novel Multifunctional Memory (MFM) unit, where a high-density two-dimensional memory array can be configured to realize different operating modes including neuromorphic computing through design or run-time configuration. Such a memory-centric computing fabric provides high flexibility and energy-efficiency for data-intensive applications by customizing to application requirements.
