Reality Simulation Systems (RSSI) was founded in 1993 at Rensselaer Polytechnic Institute’s Venture Creations, RPI’s incubator in Troy, NY by Mike Lewis. Lewis was a recent graduate of Rensselaer Polytechnic Institute. His pal and fellow graduate, Stephen (Steve) Morein graduated with him and was the lead designer of the chip. Their goal was to develop a very high-performance, cost-effective 3D graphics processors and related technology for the interactive electronic entertainment market.
The team developed a tiling design called Pixel Squirt. Microsoft’s Talisman project and VideoLogic’s PowerVR had inspired Morein; he admired the simplicity and logic of the concept.
In 1994 Lewis and Morein moved to San Jose to be in the center of action in Silicon Valley. Lewis attracted local angel investors and, in 1995, was able to raise additional capital. Lewis used the money well and enhanced the design enough to attract investors.
Lewis and Morein developed an innovative 3D architecture he named PixelSquirt, which he said offered several improvements over the traditional methods of 3D rendering. The architecture, said Lewis, addressed the bandwidth and memory requirements necessary to achieve visual realism for 3D at resolutions of 1024 × 768 and higher, the standard for high-resolution established by IBM in 1987 with the 8514/A.
In 1996 S-MOS Systems and RSSI announced a long-term joint development and marketing agreement to design 3D technology and products for personal computers.
S-MOS worked with Steve Morein to develop the SPC1515 PIX. Morein said at the time, “Even with the drop in memory prices it doesn’t pay to re-invent 2D. Instead, make it (the PIX) work with any card that supports DirectDraw surfaces.” When asked if they might take advantage of Tseng’s IMA port, Morein said they were investigating this method.
When asked who the competition is, Sandeep Gupta of S-MOS said, “Rendition, maybe, but the real competition is a pair of skates for a Christmas present.”
The competition is a pair of skates for Christmas.
RSSI didn’t do look-up-write backs to CPU and instead used 250K on-chip cache. They also developed special code that used the Pentium’s dual pipeline, more like a traditional image generator. Morein said the next version of the chip would take advantage of AGP.
For texture mapping, the SCP1515 performed point sampled texel-address calculations and supported 32 × 32 to 1024 × 1024 resolution maps. Textures were stored in the host-system memory, and the chip could manage 65,536 separate texture maps and up to 128 Mbytes of addressable texture-map data. PIX also supported PCI burst transfers.
When asked how they felt their design related to the streaming processor concept of Talisman, Morein said, “We started with tile and rejected it. They do a nice job, but it’s better if you don’t have to use them. We do texture lookup after visibility. Render into texture maps then software texture look up.”
Morein said they were able to sustain data transfer rates greater than 100 Mbytes/second over PCI, but it wouldn’t work with VGA chips that insert any ‘not-ready’ commands. At full power the chip could run at 66 Mpixels/second (Z-buffered, 640 × 480). At 800 × 600 the chip reached 45 Mpixels/second.
Under the terms of the agreement, S-MOS would provide the manufacturing (through its corporate affiliate Seiko Epson in Japan), worldwide sales, marketing, and co-development reSource:s. RSSI would provide key technology and design expertise in all phases of development. The establishment of that partnership was a breakthrough and validation for RSSI. Seiko was (and still is) a very well-respected precision technology company, and the Japanese are highly diligent in their partnerships. The last thing the 115-year-old company wanted was to be embarrassed or have their reputation damaged.
Tom Endicott, vice president of S-MOS marketing and sales then, said, “We chose to work with RSSI because of their unique and innovative approach to three-dimensional design for personal computers and their specific knowledge of the computer games market. While others were approaching the problem of 3D graphics from a workstation point of view, RSSI approached the problem from the PC user’s point of view.”
The first chip of a planned three to come out of the agreement was the SPC1515 or PIX (i.e., PixelSquirt). S-MOS said it would target games and VRML 3D. Lewis said S-MOS would use existing 2D graphics subsystem buffer memory and main memory to reduce cost and improve performance. When S-MOS forecasted the bill-of-material (BOM), they said it would be $60 for a 3D upgrade board—that would have been an aggressive price for the market segment the company was targeting. As it turned out, it was not realizable. S-MOS introduced the chip concept at the 1996 Computer Game Developers Conference, but it never got into production.
S-MOS showed simulations in May 1996 of its RSSI-based SPC1515 or PIX, a 3D rendering engine for PCs. The PIX used a system’s existing 2D graphics subsystem and buffer memory. SMOS said at the time that they expected the part the following week from its corporate manufacturing affiliate, Seiko Epson. The simulations were smooth with good looking images.
S-MOS was optimistic they would have a motherboard design win to announce soon. The PIX was the first chip of a planned three to come out from S-MOS.
Reality Simulations Systems PixelSquirt
RSSI’s frame-buffer-less PixelSquirt made by S-MOS, however, was shown at the 1995 CGDC. At the conference, RSSI’s president David Bernstein said, “Our relationship with S-MOS has created an excellent working partnership to enable the complete development and introduction of our flexible 3D graphics technology. The simplicity of RSSI designs combined with S-MOS’s first-class manufacturing facilities will allow very quick product cycles, as demanded by the PC marketplace.”
Figure 1. Pixel Squirt 3D core (Jon Peddie Research)
RSSI developed a scalable image generator which was interesting. High-performance visualization and simulation systems like flight simulators used image generators. For increased performance, it was possible to daisy-chain several PixelSquirts together. RSSI built an add-in-board with four PixelSquirts (don’t you love that name) and a master controller. The AIB accepted a video stream from a VGA board via the feature connector and then shaded polygons. It got the polygon edge information via the PCI bus. It then rendered, at 100,000 flat-shaded 400-pixel triangles/second, using a greater than 3 billion pixel/second fill rate. The AIB could deliver 2,000 triangles/frame, independent of the frame rate. The AIB offered 24-bit color with a 1-bit alpha plane and a 24-bit z-buffer. The chip supported resolutions up to 1024 x 768.Figure 1. Pixel Squirt 3D core (Jon Peddie Research)
RSSI offered the four PixelSquirts, with a DAC and a master controller chip on an AIB they called LittleSquirt, with an estimated price of under $500. Although the AIB was not appropriate for gamer’s budgets of the day, the design showed the company’s capabilities. And the price was lower than any other image generators offered. But, even with S-MOS’ support, the military and commercial aircraft companies did not feel comfortable using such a small company, so RSSI didn’t have much success in that market segment. As has been proven too many times, big companies like to deal with big companies.
In mid-1997, the company began work on a new architecture, Aquila PX, and suggested an announcement for March 1998.
Aquila PX offered high-performance 2D, 3D, and video and simultaneous NTSC/PAL TV output. Lewis said the design would deliver 100Mpixels/sec. It had a floating-point set-up engine, a 4K texture cache, a 230MHz LUT-DAC, and a non-linear 3-line flicker filter for TV output. Lewis said Aquila PX could support 1024 × 768× 16 resolution with a 1MB texture buffer in a 4MB configuration. A follow-on device, VelaTX, was a 3D-only chip that Lewis said could achieve 250 Mpixels/sec and incorporated many advanced 3D features such as anisotropic texturing. VelaTX would work in conjunction with any existing 2D graphics accelerator, Lewis claimed. The 3D cores from both devices were available for licensing.
In late 1997 Morein left RSSI and went to AMD. Aquila PX never made it out of the lab, but in 1998 the company announced its VelaTX.
Stellar is born (1997)
In late 1997 RSSI was restructured and renamed Stellar Semiconductor. With the help of Sky Capital, Stellar bought the assets of RSSI, which included a design for a new 3D chip code-named Aquila PX. Some executives left S-MOS Systems to help establish the company, including Sandeep Gupta. Gupta had been the senior product manager for graphics products at S-MOS and became Stellar’s CEO. Joseph C. Del Rio, VP of engineering and co-founder of Stellar, was the executive director of engineering at S-MOS. And Michael Lewis, the company’s CTO, was with RSSI before moving to Stellar.
The company announced itself at the Second Intellectual Property in Electronics Seminar (IP98) at the Westin Hotel on March 24th, 1998, in Santa Clara, Calif. The company had over 25 employees then and had completed two rounds of financing from venture capitalists. At that time, S-MOS was still pursuing its own course.
Due to pending patent applications, few details were available at the time. Gupta said the design could achieve high performance, high resolution, and high-quality realism. Furthermore, the architecture [like Talisman and PowerVR] did not use a z-buffer, had a real-time data flow, and used half the gates of alternative solutions. The architecture was developed in 1993 and was implemented in an AIB a year later.
Stellar had planned to develop a 3D intellectual property (IP). “We also plan to move into the fabless semiconductor business by creating, marketing, and selling graphics engines for the add-in card and motherboard desktop PC arena,” said Gupta. However, according to Gupta, the Stellar graphics accelerator would target a niche market in the 3D space. One not well served by the graphics companies of the day.
Stellar had two licensees signed up for its 3D core but would not comment on who they were. Broadcom was most likely one of them.
The company planned to introduce a proprietary 3D graphics engine in 2Q98 as a synthesized HDL netlist and claimed to have two offshore foundries qualified to build it.
The first 3D core is DirectX 5.0 compliant, and the company said it would use less than 250,000 gates and be synthesizable up to 100MHz. Stellar claimed to have proven the core twice in silicon with software drivers using Direct3D and OpenGL. Gupta said it would take Stellar less than one week to hook the existing 3D core design into a company’s device. “Because the architecture is pipelined, a company can balance the performance loading and host interface effectively,” he added.
The 3D IP core and the graphics chips used RSSI’s original PixelSquirt architecture that used a parallel processor and a multiple pipelined design. PixelSquirt’s tiling engine eliminated the need for z-buffering because it removed hidden surfaces before filtering, texture mapping, and atmospheric conditioning.
Stellar said a key advantage of its core was the ability to interface easily to existing host interface and memory controller blocks. In those cases, the host IF block was only required to provide a bus master read connection to the host CPU, and the memory controller only needed to provide a read/write interface to the memory for texture map storage. The company said the 3D core was small and highly scalable and could offer a range of price/performance options to licensees. Stellar had five patents in prosecution at the time.
VelaTX (1998)
Stellar described VelaTX as the first of a family of 3D rendering engines and based on the PixelSquirt architecture. The company claimed it could deliver 200-million-pixel/s rendering without Z buffering. z-buffer elimination, Stellar reminded everyone, reduces the requirement for fast memory. Previously PixelSquirt had been offered as a synthesizable core.
Instead of rendering one polygon at a time, the PixelSquirt rendered a pixel at a time in raster order, starting with 24-bit floating-point hidden-surface removal. The remaining operations act only on data that will go to the screen.
The chip had 2.5 Mbytes of DRAM integrated with the renderer via a 512-bit bus to speed up texture mapping. Further texture storage used external SDRAM of up to 8 Mbytes. Stellar said VelaTX would support numerous Open GL and DirectX 6 features in hardware. They would include perspective correction, specular highlighting, alpha-blend and texture blend modes, multiple fog modes, and DirectX 6 texture compression.
The design had an AGP-to-PCI bridge, P-Pipe, VIP/VMI ports, and a memory-expansion bus, enabling the chip to form a hub for multimedia expansion AIBs. The VelaTX was packaged in a 388-pin BGA and would sell for $35 each in quantities of 10,000. Stellar said they would be shipping them in the 4th quarter of 1998 or the 1st quarter of 1999.Stellar and Sican (1999)
At the 1999 intellectual property in electronics seminar (ip99) in Edinburgh, Scotland, Stellar and Sican GmbH (Hannover, Germany) announced a marketing and sales agreement. Sican, which provided cores and design services, would market, and sell Stellar’s IP cores alongside Sican’s existing library of core products Sican would also offer design services to the customer base of Stellar.
According to Valentin von Tils, vice president of design for Sican, The IP core offerings from the two companies would complement each other Sican was offering audio and video decoding, broadband media access, and bus interface cores. Adding graphics to the mix gave Sican a bigger footprint in the multimedia, communications, and networking applications segments.
Nodding his head and smiling, von Tils added, “Our combined strength will greatly enhance Sican’s ability to provide a robust set of cores for customers who are designing system-on-a-chip multimedia solutions in Europe.” The synergy combined with their design services looked like a great fit, but it would be short-lived.
Broadcom acquires Stellar (2000)
After several months of negotiations, Broadcom, a maker of high-speed communications chips, said it would acquire Stellar Semiconductor to help Broadcom moves into set-top box and handheld Internet appliance markets. “This acquisition provides Broadcom with an important piece of technology required to deliver high-end 3D games to digital set-top boxes,” said Broadcom’s CEO Henry Nicholas.
“After working with Broadcom for nearly a year, we’re excited about combining forces to address the burgeoning consumer digital entertainment market,” said Gupta.
Broadcom said it would account for the acquisition as a pooling of interest. A one-time charge would be taken in the first quarter to cover the expense related to the transaction.
Broadcom tried to use the Stellar technology in a set-top box (STB) chip but could not find many OEMs willing to pay the price for the added performance. The cable companies also didn’t have the content or bandwidth to make good use of it back then. Lewis left Broadcom a few years later and, in 2015, started Mycroft AI, an open-Source: equivalent to Amazon Echo and Google Home.
Reality Simulation Systems (RSSI) was founded in 1993 at Rensselaer Polytechnic Institute’s Venture Creations, RPI’s incubator in Troy, NY by Mike Lewis. Lewis was a recent graduate of Rensselaer Polytechnic Institute. His pal and fellow graduate, Stephen (Steve) Morein graduated with him and was the lead designer of the chip. Their goal was to develop a very high-performance, cost-effective 3D graphics processors and related technology for the interactive electronic entertainment market.
